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integrated circuit systems, inc. general description features ics9161a 9161 block diagram dual programmable graphics frequency generator 9161-a revg 10/04/00 the ics9161a is a fully programmable graphics clock generator. it can generate user-specified clock frequencies using an externally generated input reference or a single crystal. the output frequency is programmed by entering a 24-bit digital word through the serial port. two fully user- programmable phase-locked loops are offered in a single package. one pll is designed to drive the memory clock, while the second drives the video clock. the outputs may be changed on-the-fly to any desired frequency between 390 khz and 120 mhz. the ics9161a is ideally suited for any design where multiple or varying frequencies are required. this part is ideal for graphics applications. it generates low jitter, high speed pixel clocks. it can be used to replace multiple, expensive high speed crystal oscillators. the flexibility of the device allows it to generate non-standard graphics clocks. the ics9161a is also ideal in disk drives. it can generate zone clocks for constant density recording schemes. the low profile, 16-pin soic or pdip package and low jitter outputs are especially attractive in board space critical disk drives. the leader in the area of multiple output clocks on a single chip, ics has been shipping graphics frequency generators since october, 1990, and is constantly improving the phase- locked loop. the ics9161a incorporates a patented fourth generation pll that offers the best jitter performance available. ? pin-for-pin and function compatible with icd2061a dual programmable graphics clock generator memory and video clocks are individually programmable on-the-fly ideal for designs where multiple or varying frequencies are required increased frequency resolution from optional pre- divide by 2 on the m counter output enable feature available for tristating outputs independent clock outputs range from 390 khz to 120 mhz for vdd >4.75v power-down capabilities low power, high speed 0.8 cmos technology glitch-free transitions available in 16-pin, 300-mil soic or pdip package ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. extclk extsel vco output divider r=1,2,4,8,16 32,64,128 vco cmos output driver mclk oe vco divide (n) vco output divider r=1,2,4,8,16 32,64,128 vco ref divide (m) mux cmos output driver vclk d14-d20 7 d0-d3 4 d11-d13 3 ref f d14-d20 7 d4-d10 7 d0-d3 4 d11-d13 3 24 24 mclk (d0-d20) 21 21 vclk (d0-d20) 21 21 21 registers 3 address init rom por init1 init2 sel0-clk sel1-data decode logic 21 data control reg xtal osc x1 x2 pd 3-to-1 mux pscale p=2or4 ref divide (m) d4-d10 7 vco divide (n) pscale p= 2
2 ics9161a pin descriptions pin configuration r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1k l c - 0 l e sn i . e d o m g n i t a r e p o n i n i p t c e l e s k c o l c . e d o m g n i m m a r g o r p l a i r e s n i t u p n i k c o l c . d n g o t n w o d - l l u p l a n r e t n i s a h 2a t a d - 1 l e sn i s a h . e d o m g n i t a r e p o n i n i p t c e l e s k c o l c . e d o m g n i m m a r g o r p l a i r e s n i t u p n i a t a d . d n g o t n w o d - l l u p l a n r e t n i 3d d v ar w p. r e w o p 4e on i. d d v o t p u - l l u p l a n r e t n i s a h . w o l n e h w s t u p t u o s e t a t s i r t 5d n gr w p. d n u o r g 61 xn i r o f s a i b k c a b d e e f d n a e c n a t i c a p a c d a o l l a t x s e d u l c n i t u p n i s i h t . t u p n i l a t s y r c . l a t s y r c e h t 72 xt u o. e c n a t i c a p a c d a o l l a t x l a n r e t n i s e d u l c n i h c i h w t u p t u o l a t s y r c 8k l c mt u o. t u p t u o k c o l c y r o m e m 9k l c vt u o. t u p t u o k c o l c o e d i v 0 1# t u o r r et u o. d r o w d e m m a r g o r p y l l a i r e s e h t n i r o r r e n a s l a n g i s w o l t u p t u o 1 1k l c t x en i. d d v o t p u - l l u p l a n r e t n i s a h . t u p n i k c o l c l a n r e t x e 2 10 t i n in i . d n g o t n w o d - l l u p l a n r e t n i s a h . b s l , s n o i t i d n o c p u - r e w o p l a i t i n i s t c e l e s 3 1d d vr w p. r e w o p 4 11 t i n in i . d n g o t n w o d - l l u p l a n r e t n i s a h . b s m , s n o i t i d n o c p u - r e w o p l a i t i n i s t c e l e s 5 1l e s t x en i o t p u - l l u p l a n r e t n i s a h . t u p t u o k l c v s a ) k l c t x e ( t u p n i k c o l c l a n r e t x e s t c e l e s . d d v 6 1# d pn i. d d v o t p u - l l u p l a n r e t n i s a h . w o l e v i t c a , n i p n w o d - r e w o p 16-pin 300- mil soic or pdip
3 ics9161a register definitions the register file consists of the following six registers: register addressing as seen in the vclk selection table, oe acts to tristate the output. the pd# pin forces the vclk signal high while powering down the part. the extclk pin will only be multiplexed in when extsel and sel0 are logic 0 and sel1 is a logic 1. the memory clock outputs are controlled by pd# and oe as follows: the clock select pins sel0 and sel1 have two purposes. in serial programming mode, these pins act as the clock and data pins. new data bits come in on sel1 and these bits are clocked in by a signal on sel0. while these pins are acquiring new information, the vclk signal remains unchanged. when sel0 and sel1 are acting as register selects, a time-out interval is required to determine whether the user is selecting a new register or wants to program the part. during this initial time-out, the vclk signal remains at its previous frequency. at the end of this time-out interval, a new register is selected. a second time-out interval is required to allow the vco to settle to its new value. during this period of time, typically 5ms, the input reference signal is multiplexed to the vclk signal. when mclk or the active vclk register is being re- programmed, then the reference signal is multiplexed glitch- free to the output during the first time-out interval. a second time-register out interval is also required to allow the vco to settle. during this period, the reference signal is multiplexed to the appropriate output signal. the ics9161a places the three video clock registers and the memory clock register in a known state upon power-up. the registers are initialized based on the state of the init1 and init0 pins at application of power to the device. the init pins must ramp up with vdd if a logical 1 on either pin is required. these input pins are internally pulled down and will default to a logical 0 if left unconnected. the registers are initialized as follows: register initialization register selection when the ics9161a is operating, the video clock output is controlled with a combination of the sel0, sel1, pd# and oe pins. the video clock is also multiplexed to an external clock (extclk) which can be selected with the extsel pin. the vclk selection table shows how vclk is selected. vclk selection 1 t i n i0 t i n ig e r m0 g e r1 g e r2 g e r 0 0 1 1 0 1 0 1 0 0 5 . 2 3 0 0 0 . 0 4 0 5 3 . 0 5 4 4 6 . 6 5 5 7 1 . 5 2 5 7 1 . 5 2 0 0 0 . 0 4 0 0 0 . 0 4 2 2 3 . 8 2 2 2 3 . 8 2 2 2 3 . 8 2 0 5 3 . 0 5 2 2 3 . 8 2 2 2 3 . 8 2 2 2 3 . 8 2 0 5 3 . 0 5 e o# d pl e s t x e1 l e s0 l e sk l c v 0 1 1 1 1 1 1 x 0 1 1 1 1 1 x x x x 0 1 x x x 0 0 1 1 1 x x 0 1 0 x 1 e t a t s i r t h g i h d e c r o f 0 g e r 1 g e r k l c t x e 2 g e r 2 g e r e o# d pk l c m 0 1 1 x 1 0 e t a t s i r t g e r m n w d r w p mclk selection s s e r d d a ) 0 a - 2 a ( r e t s i g e rn o i t i n i f e d 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 g e r 1 g e r 2 g e r g e r m n w d r w p g e r l t n c 1 r e t s i g e r k c o l c o e d i v 2 r e t s i g e r k c o l c o e d i v 3 r e t s i g e r k c o l c o e d i v r e t s i g e r y r o m e m e d o m n w o d - r e w o p r o f r o s i v i d r e t s i g e r l o r t n o c
4 ics9161a control register definitions the control register allows the user to adjust various internal options. the register is defined as follows: t i be m a n t i be u l a v t l u a f e dn o i t p i r c s e d 1 25 c0 . t n e m e l p m i l l i w n i p # d p e h t e d o m n w o d - r e w o p h c i h w s e n i m r e t e d t i b s i h t e h t f o n o i t c n u f a e b o t s l a n g i s k l c m e h t s e c r o f , 0 = 5 c , 1 e d o m n w o d - r e w o p d n a l a t s y r c e h t f f o s n r u t , 1 = 5 c , 2 e d o m n w o d - r e w o p . r e t s i g e r n w o d - r e w o p . s t u p t u o l l a s e l b a s i d 0 24 c0 y c n e u q e r f g n i r u d k l c v o t d e x e l p i t l u m s i k c o l c h c i h w s e n i m r e t e d t i b s i h t 1 = 4 c . t u p t u o k l c v e h t o t y c n e u q e r f e c n e r e f e r e h t s e x e l p i t l u m 0 = 4 c . s e g n a h c s c i h p a r g e h t e r e h w s n o i t a c i l p p a r o f t u p t u o k l c v e h t o t k l c m s e x e l p i t l u m f s a w o l s s a n u r t o n n a c r e l l o r t n o c . f e r 9 13 c0 s i l a v r e t n i t u o - e m i t e h t . l a v r e t n i t u o - e m i t e h t f o h t g n e l e h t s e n i m r e t e d t i b s i h t , s e m e r t x e n i a t r e c o t d e m m a r g o r p s i o c v s i h t f i . o c v k l c m e h t m o r f d e v i r e d d e l b u o d , 1 = 3 c . t u o - e m i t l a m r o n , 0 = 3 c . t r o h s o o t e b y a m l a v r e t n i t u o - e m i t e h t . l a v r e t n i t u o - e m i t 8 12 c0 . 0 o t t e s e b t s u m , d e v r e s e r 7 11 c1 . e m i t h g i h t u p t u o n i e s a e r c e d s n 1 a s e s u a c 0 = 1 c . e l c y c y t u d e h t s t s u j d a t i b s i h t n a c t n e m t s u j d a e h t , h g i h s i e c n a t i c a p a c d a o l e h t f i . t n e m t s u j d a o n s e s u a c 1 = 1 c . % 0 5 o t r e s o l c e l c y c y t u d e h t g n i r b 6 10 c0 . 0 o t t e s e b t s u m , d e v r e s e r 5 12 s n0 p e h t s e l a c s e r p 1 = 2 s n . 2 y b r e t n u o c n e h t s e l a c s e r p 0 = 2 s n . 2 r e t s i g e r n o s t c a . 4 o t e u l a v r e t n u o c 4 11 s n0 p e h t s e l a c s e r p 1 = 1 s n . 2 y b r e t n u o c n e h t s e l a c s e r p 0 = 1 s n . 1 r e t s i g e r n o s t c a . 4 o t e u l a v r e t n u o c 3 10 s n0 p e h t s e l a c s e r p 1 = 0 s n . 2 y b r e t n u o c n e h t s e l a c s e r p 0 = 1 s n . 0 r e t s i g e r n o s t c a . 4 o t e u l a v r e t n u o c
5 ics9161a serial programming architecture the pins sel0 and sel1 perform the dual functions of select- ing registers and serial programming. in serial programming mode, sel0 acts as a clock pin while sel1 acts as the data pin. the ics9161a-01 may not be serially programmed when in power-down mode. in order to program a particular register, an unlocking sequence must occur. the unlocking sequence is detailed in the following timing diagram: serial data register the serial data is clocked into the serial data register in the order described in figure 1 below (serial data timing). the serial data is sent as follows: an individual data bit is sampled on the rising edge of clk. the complement of the data bit must be sampled on the previous falling edge of clk. the setup and hold time requirements must be met on both clk edges. for specifics on timing, see the timing diagrams on pages 10, 11 and 12. the bits are shifted in this order: a start bit, 21 data bits, 3 address bits (which designate the desired register), and a stop bit. a total of 24 bits must always be loaded into the serial data register or an error is issued. following the entry of the last data bit, a stop bit or load command is issued by bringing data high and toggling clk high-to-low and low-to-high. the unlocking mechanism then resets itself following the load. only after a time-out period are the sel0 and sel1 pins allowed to return to a register selection function. since the vclk registers are selected by the sel0 and sel1 pins, and since any change in their state may affect the output frequency, new data input on the selection bits is only permitted to pass through the decode logic after the watchdog timer has timed out. this delay of sel0 or sel1 data permits a serial program cycle to occur without affecting the current register selection. the unlock sequence consists of at least five low-to-high transitions of clk while data is high, followed immediately by a single low-to-high transition while data is low. following this unlock sequence, data can be loaded into the serial data register. this programming must include the start bit, shown in figure 1. following any transition of clk or data, the watchdog timer is reset and begins counting. the watchdog timer ensures that successive rising edges of clk and data do not violate the time-out specification of 2ms. if a time-out occurs, the lock mechanism is reset and the data in the serial data register is ignored. figure 1: serial data timing
6 ics9161a the serial data register is exactly 24 bits long, enough to accept the data being sent. the stop bit acts as a load command that passes the contents of the serial data register into the register indicated by the three address bits. if a stop bit is not received after the serial register is full, and more data is sent, all data in the register is ignored and an error issued. if correct data is received, then the unlocking mechanism re-arms, all data in the serial data register is ignored, and an error is issued. errout# operation any error in programming the ics9161a is signaled by errout#. when the pin goes low, an error has been detected. it stays low until the next unlock sequence. the signal is invoked for any of the following errors: incorrect start bit, incorrect data encoding, incorrect length of data word, and incorrect stop bit. programming the ics9161a the ics9161a has a wide operating range, but it is recommended that it is operated within the following limits: 3.15v< v dd <5.25v v dd supply voltage 1 mhz 7 ics9161a power management issues power-down mode 1 the ics9161a contains a mechanism to reduce the quiescent power when stand-by operation is desired. power-down mode 1 is invoked by polling pd# low and having the proper cntl register bit set to zero. in this mode, vcos are shut down, the vclk output is forced high, and the mclk output is set to a user-defined low frequency value to refresh dynamic ram. the power-down mclk value is determined by the following equation: mclk pd = f ref /(pwrdwn register divisor value) the power-down register divisor is determined according to the 4-bit word programmed into the pwrdwn register (see table below). power-down mode 2 when there is no need for any output during power-down, an alternate mode is available which will completely shut down all outputs and the reference oscillator, but still preserves all register contents. power-down mode 2 in invoked by first programming the power-down bit in the cntl register and then pulling the pd# pin low. the pd# pin the pd# pin has a standard internal pull-up resistor during normal operation. when the chip goes into power-down mode 1 or 2, the normal pull-up resistor is dynamically switched to a weak pull-up, which reduces power consumption. if the pd# pin is allowed to float after it has been pulled down, the weak pull-up will bring the signal high and allow the device to resume operation. power-down register table s t i b n w d r w pn w d r w pn w o d - r e w o pd p k l c m 3 p2 p1 p0 pe u l a v r e t s i g e rr o s i v i df ( f e r ) 8 1 8 1 3 . 4 1 = 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 ) t l u a f e d ( 8 9 a b c d e f a / n 2 3 0 3 8 2 6 2 4 2 2 2 0 2 8 1 6 1 4 1 2 1 0 1 8 6 4 a / n z h k 4 . 7 4 4 z h k 3 . 7 7 4 z h k 4 . 1 1 5 z h k 7 . 0 5 5 z h k 6 . 6 9 5 z h k 8 . 0 5 6 z h k 9 . 5 1 7 z h k 5 . 5 9 7 z h k 9 . 4 9 8 z h m 2 0 . 1 z h m 9 1 . 1 z h m 3 4 . 1 z h m 9 7 . 1 z h m 9 3 . 2 z h m 8 5 . 3
8 ics9161a absolute maximum ratings note 1: parameter is guaranteed by design and characterization. not 100% tested in production. vdd referenced to gnd ............................................... 7v operating temperature under bias (t oper ) .................... 0c to 70c storage temperature ...................................................... -40c to +150c max. soldering temperature (10 sec) (t sol ) ................ +260c voltage on i/o pins referenced to gnd ........................ gnd -0.5v to vdd +0.5v junction temperature (t j ) .............................................. +125c power dissipation ........................................................... 0.35 watts stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics at 5.0v v dd = +5v 5%, 0c t ambient +70c s c i t s i r e t c a r a h c c d r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u e g a t l o v t u p n i l e v e l h g i hv h i 0 . 2--v e g a t l o v t u p n i l e v e l w o lv l i -- 8 . 0v e g a t l o v t u p t u o s o m c l e v e l h g i h 1 v h o i h o a m 4 - =4 8 . 3--v e g a t l o v t u p t u o l e v e l w o l 1 v l o i l o a m 4 =--4 . 0v t n e r r u c h g i h t u p n ii h i v d d v = h i - l l u p r o f v 5 2 . 5 = s n w o d -- 0 0 1a t n e r r u c w o l t u p n ii l i v l i s p u - l l u p r o f v 0 =0 5 2 ---a t n e r r u c e g a k a e l t u p t u oi z o ) e t a t s i r t (0 1 --0 1a t n e r r u c y l p p u s r e w o pi d d 5 1-5 6a m ) l a c i p y t ( t n e r r u c y l p p u s r e w o pi p y t - d d z h m 0 6 @-5 3-a m t n e r r u c y l p p u s r e w o p g o l a n ai d d a -- 0 2a m ) 1 e d o m ( t n e r r u c n w o d - r e w o pi 1 d p -6 5 . 7a m ) 2 e d o m ( t n e r r u c n w o d - r e w o pi 2 d p -5 20 5a e c n a t i c a p a c t u p n i 1 c n i -- 0 1f p
9 ics9161a electrical characteristics at 5.0v (continued) notes: 1. parameter guaranteed by design and characterization. not 100% tested in production. 2. for reference frequencies other than 14.81818 mhz, the pre-loaded rom frequencies will shift proportionally. 3. duty cycle is measured at cmos threshold levels. at 5 volts, v th =2.5 volts. 4. if the interval is too short, see the time-out interval section in the control register definition. s c i t s i r e t c a r a h c c a n o i t p i r c s e de m a nl o b m y sn i mp y tx a ms t i n u e u l a v r o t a l l i c s o e c n e r e f e r 2 e c n e r e f e r y c n e u q e r f f f e r 18 1 8 1 3 . 4 10 6z h m f / 1 f e r d o i r e p e c n e r e f e rt f e r 6 . 6 18 0 4 8 . 9 60 0 0 1s n r o t a l l i c s o t u p n i e h t r o f e l c y c y t u d t s a d e n i f e d 1 t / f e r e l c y c y t u d t u p n it 1 % 5 2-% 5 7- s e u l a v r o t a l l i c s o t u p t u o k c o l c t u p t u o s d o i r e p t 2 0 2 1 ( 3 3 . 8 ) z h m - 0 9 3 ( 4 6 5 2 ) z h k s n s r o t a l l i c s o t u p t u o e h t r o f e l c y c y t u d 3 e l c y c y t u d t u p t u ot 3 % 5 4-% 5 5- a o t n i s r o t a l l i c s o t u p t u o e h t r o f e m i t e s i r d a o l f p 5 2 s e m i t e s i rt 4 --3 s n a o t n i s r o t a l l i c s o t u p t u o e h t r o f e m i t l l a f d a o l f p 5 2 s e m i t l l a ft 5 --3 s n t u p t u o y c n e u q e r f d l ot u p t u o 1 q e r ft 1 q e r f ---- t u p t u o y c n e u q e r f w e nt u p t u o 2 q e r ft 2 q e r f ---- e l i h w h g i h s n i a m e r t u p t u o k c o l c e m i t y c n e u q e r f e c n e r e f e r o t s e x u m t u p t u o f f e r e m i t x u mt a t 5 . 0 f e r -t 5 . 1 f e r s n r o f d n a g n i m m a r g o r p l a i r e s r o f l a v r e t n i e l t t e s o t s e g n a h c o c v 4 l a v r e t n i t u o - e m i tt t u o - e m i t 25 0 1s m e l i h w h g i h s n i a m e r t u p t u o k c o l c e m i t e u l a v y c n e u q e r f w e n o t s e x u m t u p t u o t 2 q e r f e m i t x u mt b t 5 . 0 f e r t 5 . 1 f e r -s n o t n i o g o t s r o t a l l i c s o t u p t u o e h t r o f e m i t l a n g i s - s i d t u o r e t f a e d o m e t a t s i r t n o i t r e s s a e t a t s i r tt 6 -5 2-s n r e v o c e r o t s r o t a l l i c s o t u p t u o e h t r o f e m i t l a n g i s - s i d t u o r e t f a e d o m e t a t s i r t m o r f h g i h s e o g d i l a v k l ct 7 -2 1-s n n o i t a r e p o f o e d o m n w o d - r e w o p r o f e m i t t c e f f e e k a t o t n w o d - r e w o pt 8 -5 2-s n n w o d - r e w o p m o r f y r e v o c e r r o f e m i t k l c d i l a v a o t e d o m p u - r e w o pt 9 -2 1-s n r e t f a h g i h o g o t k l c m r o f e m i t h g i h d e t r e s s a s i n w d r w p h g i h t u o k l c mt 0 1 0-t n w d r w p s n f o t r o i r p k l c m f o y a l e d k l c m t a l a n g i s t u p t u o y a l e d t u o k l c mt 1 1 t 5 . 0 k l c m -t 5 . 1 k l c m s n k c o l c l a i r e s f o d o i r e p k c o l ct k l c r e s t 2 f e r -2 s m e m i t p u - t e st u s 0 2--s n e m i t d l o ht d h 0 1--s n d n a m m o c d a o lt d m c d l 0-t 1 0 3 +s n
10 ics9161a rise and fall times tristated timing
11 ics9161a selection timing mclk and active vclk register programming timing
12 ics9161a soft power-down timing (mode 2) serial programming timing
13 ics9161a general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1) all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf rc termination should be used on all over 50mhz outputs. 3) optional crystal load capacitors are recommended. capacitor values: c1, c2 : crystal load values determined by user c3 : 100pf ceramic all unmarked capacitors are 0.01f ceramic connections to vdd:
14 ics9161a ordering information ics9161a-01cn16 example: ics xxxx - ppp m x#w prefix ics, av=standard device device type (consists of 3 or 4 digit numbers) pattern number (2 or 3 digit number for parts with rom code patterns, if applicable) package type n=dip (plastic) lead count & package width lead count=1, 2 or 3 digits w=.3? soic or .6? dip; none=standard width 16-pin pdip package
15 ics9161a soic package (wide body) ordering information ics9161a -01cw16 package type w=soic example: ics xxxx - ppp m x#w lead count & package w idth lead count=1, 2 or 3 digits w=.3? soic or .6? dip; none=standard width pattern number (2 or 3 digit number for parts with rom code patterns, if applicable) prefix ics, av = standard device device type (consists of 3 or 4 digit numbers) t n u o c d a e ll 6 1 l n o i s n e m i d4 0 4 . 0 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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